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rev. 3.0 may 2018 www.aosmd.com page 1 of 13 AOZ5019 high-current, high-performance drmos power module general description the AOZ5019 is a high efficiency synchronous buck power stage module consisting of two asymmetrical mosfets and an integrated driver. the mosfets are individually optimized for operation in the synchronous buck configuration. the high side mosfet has low capacitance and gate charge for fast switching with low duty cycle operation. the low side mosfet has ultra low r ds(on) to minimize conduction losses. the AOZ5019 is intended for use with ttl and tri-state compatible, which allows both power mosfets to be turned off. a number of features are provided making the AOZ5019 a highly versatile power module. the boot supply diode is integrated in the driver. the low side mosfet can be driven into diode emulation mode to provide asynchronous operation when required. the pin-out is optimized for low inductance routing of the converter keeping the parasitics and their effects to the minimum. features ? 4.5 v to 25 v input voltage range ? 4.5 v to 5.5 v driver supply range ? up to 30 a output current ? up to 1.5 mhz pwm operation ? tri-state pwm input ? undervoltage protection ? integrated boot supply diode ? diode emulation mode of operation ? small 5x3.5 qfn-23l package applications ? servers ? notebook computers ? vrms for motherboards ? point of load dc/dc converters ? memory and graphic cards ? video gaming consoles typical application circuit +5v cgnd vout pgnd vin 5v to 25v vcc pwm smod en boot vin cboot lout cin cout pgnd cgnd vswh AOZ5019 pwm controller drive logic and dead time control not recommended for new designs
AOZ5019 rev. 3.0 may 2018 www.aosmd.com page 2 of 13 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/media/aosgreenpolicy.pdf for additional information . pin configuration part number ambient temperature range package environmental AOZ5019qi -40 c to +85 c 5x3.5 qfn-23l green product vin vin vin pgnd pgnd pgnd pgnd pwm en vin cgnd gl pgnd pgnd 5x3.5 qfn-23 (top view) smod vcc boot gh vswh 1 vswh vswh vswh vswh vin pgnd
AOZ5019 rev. 3.0 may 2018 www.aosmd.com page 3 of 13 pin description functional block diagram pin number pin name pin function 1 smod skip mode input. when the pin is held active low, diode emulation or skip mode is enabled for the ls fet. 2 vcc control and driver supply input. nominal 5 v. 3 boot gate drive supply for the hs fet. nominal 5 v. the bootstrap diode is internal to the module. connect a 0.1 ? f or higher ceramic capacitor between vswh node at pin 5. 4 gh gate of the hs fet. used for module test ing during production. no user connections. 5 vswh switching or phase node connected to source of high side mosfet and drain of the low side mosfet. electrically attached to the ls fet dr ain tab, this pin is dedicated for boot cap connection and needs to be connected to pin 13 externally on pcb. 6, 7, 8 vin power input to the switching mosfets. attached to the hs fet drain tab. 9, 10, 11, 12, 17, 18 pgnd power ground. 13, 14, 15, 16 vswh switching or phase n ode connected to source of high side mosfet and drain of the low side mosfet. electrically attached to the ls fet drain tab. 19 gl gate of the ls fet. used for module testing during production. no user connections. 20 cgnd control or analog ground for return of control signals and bypass capacitors. 21 vin power input to the switching mosfet s. attached to the hs fet drain tab. 22 en disable pin for the controller . both gates are held active low when en is grounded. 23 pwm pulse width modulated tri-state input from external controller. vcc boot vin vswh pgnd pwm en smod vcc cgnd vcc uvlo complementary control logic shoot through control
AOZ5019 rev. 3.0 may 2018 www.aosmd.com page 4 of 13 absolute maximum ratings exceeding the absolute maximum ratings may damage the device. notes: 1. peak voltages can be applied for 100 ns per switching cycle. 2. devices are inherently esd sens itive, handling precautions are required. human body model rating: 1.5 k ? in series with 100 pf. recommended operating conditions the device is not guaranteed to operate beyond the maximum recommended operating conditions. electrical characteristics (3) t a = 25c, v in = 12v, v cc = 5 v unless otherwise specified. parameter rating supply voltage (vin) -0.3 v to 30 v switch node voltage (vswh) -0.3 v to 30 v switch node voltage transient (1) 38v bootstrap voltage (vboot) -0.3 v to 30 v vboot voltage transient (1) 40 v supply and gate drive voltages: {vcc, (vboot ? vswh)} -0.3 v to 7 v control inputs (pwm, smod, en) -0.3 v to vcc +0.3 v storage temperature (t s ) -65 c to +150 c junction temperature (t j )150 c esd rating (2) 2 kv parameter rating supply voltage (vin) 4.5 v to 25 v supply and gate drive voltages {vcc, (vboot ? vswh)} 4.5 v to 5.5 v control inputs (pwm, smod, en) 0 v to vcc ? 0.3 v operating frequency 200 khz to 1.5 mhz symbol parameter conditions min. typ. max. units vin operating voltage 4.5 25 v vcc 4.5 5.5 v r ? jc (4) thermal resistance pcb temp = 100 c 3 c / w r ? ja (4) aos evaluation board 10 c / w input supply and uvlo v cc undervoltage lockout v cc rising 3.5 3.9 v v cchyst 550 mv i vcc control circuit bias current en = 0, vcc = 5 v 50 75 ? a en = high, v pwm = open 350 500 ? a en = high, v pwm = 0 v 650 ? a i vc drive circuit operating current en = high, v pwm = 300 khz @ 50% 25 ma en = high, v pwm = 1 mhz @ 50% 60 ma pwm input v pwmh pwm input high threshold v pwm rising, vcc = 5 v 3.6 3.9 4.1 v v pwml pwm input low threshold v pwm falling, vcc = 5 v 0.8 1.0 1.2 v i pwm pwm pin input current source or sink, v pwm = 0 v to 5 v 250 ? a v trih pwm input tri-state threshold v pwm rising, vcc = 5 v 1.0 1.3 1.6 v v tril v pwm falling, vcc = 5 v 3.4 3.7 4.0 v v trrh tri-state threshold hysteresis v pwm rising, vcc = 5 v 280 mv v trfh v pwm falling, vcc = 5 v 170 mv
AOZ5019 rev. 3.0 may 2018 www.aosmd.com page 5 of 13 notes: 4. all voltages are specified with respect to the corresponding gnd pin 5. characterisation value. not tested in production. en input v enon outputs enable threshold vcc = 5 v 2.0 v v enoff outputs disable threshold vcc = 5 v 0.8 v i en en pin input current source or sink 10 ? a smod input v smodh smod enable threshold vcc = 5 v 2.0 v v smodl smod disable threshold vcc = 5 v 0.8 v i smod smod pin input current source or sink 10 ? a gate driver timings t pdlu pwm to hs gate pwm h ? l, gh h ? l18ns t pdll pwm to ls gate pwm l ? h, gl h ? l25ns t pdhu ls to hs gate deadtime gl h ? l, gh l ? h20ns t pdhl hs to ls gate deadtime gh h ? l, gl l ? h20ns t tsshd tri-state shutdown delay 150 ns t pts tri-state propagation delay 35 ns symbol parameter conditions min. typ. max. units electrical characteristics (3) (continued) t a = 25c, v in = 12v, v cc = 5 v unless otherwise specified.
AOZ5019 rev. 3.0 may 2018 www.aosmd.com page 6 of 13 typical performance characteristics unless otherwise noted, v cc = 5 v, f sw = 800 khz, l out = 200 nh, v out = 1.8 v, i out = 20 a, module loss measured on aos evaluation board at t a = 25 c natural convection. module loss does not include inductor loss. 33 31 29 27 25 23 21 19 4.3 4.5 4.7 4.9 5.1 5.3 5.5 5.5 vcc (volts) ivcc (mamps) fig 2. output current vs. temperature fig 1. module loss vs. load current fig 5. ivcc vs. vcc fig 6. ivcc vs. frequency fig 3. normalised module loss vs. vcc fig 4. normalised module loss vs. input voltage 7 6 5 4 3 2 1 0 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 3 5 7 9 111315171921 15 510 2025 load current (amps) loss (watts) module loss (normalised) 12 vin 500khz 19 vin 800khz input voltage (volts) 35 30 25 20 15 10 5 0 06080 20 40 100 120 140 temperature (c) current (a) vin = 12v vout = 1.8v f = 500khz l = 0.2h 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 4.5 4.6 4.8 4.9 5.0 4.7 5.1 5.2 5.3 5.4 5.5 module loss (normalised) vcc (volts) 50 45 40 35 30 25 20 15 10 0.3 0.5 0.7 0.9 1.1 1.3 1.5 switch frequency (mhz) ivcc (mamps)
rev. 3.0 may 2018 www.aosmd.com page 7 of 13 AOZ5019 typical performance characteristics (continued) fig 9. pwm input threshold vs. temperature fig 10. pwm input tri state hold off time vs. temperature fig 11. en input threshold vs. temperature fig 12. smod input threshold vs. temperature temperature (c) smod threshold (volts) fig 7. ivcc vs. temperature 1.8 1.7 1.6 1.5 1.4 1.3 1.2 -40 -20 0 20 40 60 80 100 120 140 temperature (c) ivcc (mamps) 1.035 1.030 1.025 1.020 1.015 1.010 1.005 1.000 0.995 0.990 -40 -20 0 20 40 60 80 100 120 140 temperature (c) vcc threshold (volts) vcc rising threshold vcc falling threshold 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 -40 -20 0 20 40 60 80 100 120 140 i out = 0a temperature (c) pwm threshold (volts) enable threshold (volts) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -40 -20 0 20 40 60 80 100 120 140 pwm rising threshold pwm falling threshold fig 8. vcc uvlo threshold vs. temperature temperature (c) tri state hold off time (ns) 240 220 200 180 160 140 120 -40 -20 0 20 40 60 80 100 120 140 temperature (c) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 -40 -20 0 20 40 60 80 100 120 140 en ramp down en ramp up i out = 0a smod threshold high smod threshold low i out = 0a
rev. 3.0 may 2018 www.aosmd.com page 8 of 13 AOZ5019 timing diagram figure 13. timing diagram application information AOZ5019qi is a fully integrated power module designed to work over an input voltage range of 4.5 v to 25 v with 5 v supplies for gate drive and internal control circuits. a number of features are provided making the AOZ5019qi a highly versatile power module. high side and low side power mosfets are combined in one package with the pin outs optimized for power routing with minimum parasitic inductances. the mosfets are individually tailored for efficient operation as either high side or low side switches in a low duty cycle synchronous buck converter. a high current driver is also included in the package which minimizes the gate drive loop and results in extremely fast switchin g. the modules are fully compatible with intel drmos specification rev 4.0 in form fit and function. powering the module and the gate drives an external supply vcc of 5 v is required for driving the mosfets. the mosfets are designed with low gate thresholds so that lower drive voltage can be used to reduce the switching and drive losses without compromising the conduction losses. the integrated gate driver is capable of supplying several amperes of peak current into the ls fet to achieve extremely fast switching. a ceramic bypass capacitor of 1 ? f or higher is recommended from vcc to cgnd. for effective filtering it is strongly recommended to have a direct connection from this capacitor to cgnd, see figure 14. the boost supply for driving the high side mosfet is generated by connecting a small capacitor between boot pin and the switching node vswh. it is recommended that this capacitor cboot be connected as close as possible to the devi ce across pins 3 and 5. boost diode is integrated into the package. rboot is an optional resistor used by designers to slow down the turn on speed of the high side mosfet. the value is a compromise between the need to keep both the switching time and vswh node spikes as low as possible and is typically 1 ? to 5 ? ? undervoltage lockout and enable vcc is monitored for uvlo conditions and both outputs are actively held low unless adequate gate supply is available. the under-voltage lockout is set at 3.5 v with a 550 mv hysteresis. since the pwm control signals are provided typically from an external controller or a digital processor extra care must be taken during start up. the AOZ5019qi must be powered up and enabled before the pwm input is applied. it should be ensured that pwm signal goes through a proper soft start sequence to minimize inrush current in the converter during start up. powering t he module with a full duty cycle pwm signal already applied may lead to a number of undesirable consequences as explained below. outputs can also be turned off through the disb pin. when this input is grounded the drivers are disabled and held active low. the module is in standby mode with low quiescent current of less than 75 ? a. pwm gh gl t pdll t pdlu t tsshd t tsshd t pts t pts t pdhl t pdhu pwm tri state band
AOZ5019 rev. 3.0 may 2018 www.aosmd.com page 9 of 13 important: if the en is used it is necessary to ensure proper coordination with soft start and enable features of the external pwm controller in the system. every time AOZ5019qi is disabled th rough en there will be no output and the external c ontroller may enter into open loop and put out a pwm signal with maximum duty ratio possible. if the AOZ5019qi is re-enabled by taking en high, there will be extremely large inrush currents while the output voltage builds up again which may drive the system into current limit. there might be undesirable consequences such as inductor saturation, overloading of the input or even a catastrophic failure of the device. it is recommended that the pwm controller be disabled when AOZ5019qi is disabled or non operational because of uvlo. the pwm co ntroller should always be enabled with a soft start to minimize stresses on the converter. in general it should be noted that AOZ5019qi is a combination of two mosfets with an unintelligent driver, all of which are optimized for switching at the highest efficiency. other than uvlo and thermal protection, it does not have any monitoring or protection functions built in. the pwm controller should be designed in to perform these functions under all possible operating and transient conditions. input voltage vin AOZ5019qi is rated to operate over a wide input range of 4.5 v to 25 v. as with any other synchronous buck converter, large pulse currents at high frequency and extremely high di/dt rates will be drawn by the module during normal operation. it is strongly recommended to bypass the input supply very close to package leads with x7r or x5r quality ceramic capacitors. the high side mosfet in AOZ5019qi is optimized for fast switching with low duty ratios. it has ultra low gate charges which have been achieved as a trade off with higher r ds(on) value. when the module is operated at low vin the duty ratio will be higher a nd conduction losses in the hs fet will also be correspondingly higher. this will be compensated to some extent by reduced switching losses. the total po wer loss in the module may appear to be low even though in reality the hs mosfet losses may be disproportiona tely high. since the two mosfets have their own exposed pads and pcb copper areas for heat dissipation, the hs fet may be much hotter than the ls fet. it is recommended that worst case junction temperature be measured and ensured to be within safe limits when the module is operated with high duty ratios. pwm input AOZ5019qi is offered in two versions which can be interfaced with pwm logic co mpatible with either 5 v (ttl) or 3v (cmos). refer to figure 13 for the timing and propagation delays between the pwm input and the gate drives. the pwm is also a tri-state compatible input. when the input is high impedance or unconnected both the gate drives will be off and the gates are held active low. the pwm threshold table (table 1) lists the thresholds for high and low level transitions as well as tri- state operation. as shown in figure 13, there is a hold off delay between the time pwm si gnal enters the tri-state window and the corresponding gate drive is pulled low. this delay is typically 170 ns and intended to prevent spurious triggering of the tri-state mode which may be caused either by noise induced glitches in the pwm waveform or slow rise and fall times. table 1. pwm input and tri-state thresholds note: see figure 13 for propagation delays and tri-state window. diode mode emulation of low side mosfet (smod) AOZ5019qi can be operated in the diode emulation or skip mode using the smod pin. this is useful if the converter has to operate in asynchronous mode during start up, light load or under pre bias conditions. if smod is taken high, the controlle r will use the pwm signal as reference and generate both the high and low side complementary gate drive outputs with the minimal delays necessary to avoid cross conduction. when the pin is taken low the hs fet drive is not affected but diode emulation mode is activated for the ls fet. see table 2 for a comprehensive view of all logic inputs and corresponding drive conditions. table 2. control logic truth table note: diode emulation mode is activa ted when smod pin is held low. thresholds ? v pwmh v pwml v trih v tril AOZ5019qi 3.9 v 1.0 v 1.3 v 3.7 v en smod pwm gh gl lxx l l hl h h l hl l lsee note hxtri-statel l hh h h l hh l l h
AOZ5019 rev. 3.0 may 2018 www.aosmd.com page 10 of 13 gate drives AOZ5019qi has an internal high current high speed driver that generates the floating gate drive for the hs fet and a complementary drive for the ls fet. propagation delays between transitions of the pwm waveform and corresponding gate drives are kept to the minimum. an internal shoot through protection scheme ensures that neither mosfet turns on while the other one is still conducting, thereb y preventing shoot through condition of the input current. when the pwm signal makes a transition from h to l or l to h, the corresponding gate drive gh or gl begins to turn off. the adaptive timing circuit monitors the falling edge of the gate voltage and when the level goes below 1v, the complementary gate driver is turned on. the dead time between the two switches is mi nimized, at the same time preventing cross conduction across the input bus. the adaptive circuit also monitors the switching node vswh and ensures that transition from one mosfet to another always takes place without cross conduction, even under transient and abnormal conditions of operation. the gate pins gh and gl are brought out on pins 4 and 19 respectively. however these connections are not made directly to mosfet gate pads and their voltage measurement may not reflect the actual gate voltage applied inside the package. the gate connections are primarily for functional tests during manufacturing and no connections should be made to them in the application. pcb layout guidelines AOZ5019 is a high current module rated for operation up to 1.5 mhz. this requires extremely fast switching speeds to keep the switching losses and device temperatures within limits. ha ving a robust gate driver integrated in the package eliminates driver-to-mosfet gate pad parasitics of the package or pcb. while excellent switching speeds are achieved, correspondingly high levels of dv/dt and di/dt will be observed throughout the power train which requires careful attention to pcb la yout to minimize voltage spikes and other transients. as with any synchronous buck converter layout, the critical requirement is to minimize the area of the primary switching current loop, formed by the hs fet, ls fet and the input bypass capacitor cin. the pcb design is somewhat simplified because of the optimized pin out in AOZ5019qi. the bulk of vin and pgnd pins are located adjacent to each other and the input bypass ca pacitors should be placed as close as possible to t hese pins. the area of the secondary switching loop, formed by ls fet, output inductor and output capacitor cout is the next critical parameter, this requires second layer or ?inner 1? should always be an uninterrupted gnd plane with sufficient gnd vias placed as close as possible to by-pass capacitors gnd pads. mosfets in the package are directly attached to individual exposed pads, vin and pgnd to simplify thermal management. using vias, both vin and gnd pads should be attached to vin and gnd plane directly as shown below . thermal reliefs should be avoided to ensure proper heat dissipation to the board. vcc by-pass capacitor cvcc should connect directly to cgnd as shown below, use a via to connect cgnd directly to gnd, connect cboot and rboot directly to pins 3 and 5. figure 14 illustrates the vari ous copper pours and bypass capacitor locations. figure 14. pcb layout illustration rb cb
AOZ5019 rev. 3.0 may 2018 www.aosmd.com page 11 of 13 package dimensions, qfn3.5x5_23l ep2_s d top view side view bottom view note: controlling dimension are in millimeters. converted inch dimensions are not necessarily exact. e pin #1 dot by marking e1 side view a2 a1 recommended land pattern 1.850 1.325 0.725 0.331 1.225 1.85 1.30 1.13 1.11 0.000 1.12 1.85 2.175 1.069 0.375 0.000 0.375 2.125 2.600 1.924 1.699 0.175 0.325 1.855 2.050 2.600 unit: mm dimensions in millimeters dimensions in inches symbols min. typ. max. 0.50 a a1 a2 e e1 e2 d1 d l l1 l2 l3 l4 l5 b d f e 1.00 0.00 4.90 1.63 1.15 1.65 3.40 0.35 0.22 0.30 0.58 1.02 0.58 0.20 0.33 0.70 1.10 - 0.2 ref 5.00 1.73 1.25 1.75 3.50 0.40 0.27 0.35 0.63 1.12 0.63 0.25 0.38 0.75 0.50 bsc 1.20 0.05 5.10 1.83 1.35 1.85 3.60 0.45 0.32 0.40 0.68 1.22 0.68 0.30 0.43 0.80 symbols min. typ. max. a a1 a2 e e1 e2 d1 d l l1 l2 l3 l4 l5 b d f e 0.039 0.000 0.193 0.064 0.045 0.065 0.134 0.014 0.009 0.012 0.023 0.040 0.023 0.008 0.013 0.028 0.043 - 0.008 ref 0.197 0.068 0.049 0.069 0.138 0.016 0.011 0.014 0.025 0.044 0.025 0.010 0.015 0.030 0.02 bsc 0.047 0.002 0.201 0.072 0.053 0.073 0.142 0.018 0.013 0.016 0.027 0.048 0.027 0.012 0.017 0.031 a e2 l l2 l1 l3 l5 d1 l4 d f e b c 0.25
rev. 3.0 may 2018 www.aosmd.com page 12 of 13 AOZ5019 tape and reel dimens ions, qfn3.5x5_23l ep2_s package qfn3.5x5 (12mm) a0 b0 k0 e e1 e2 d0 d1 p0 p1 p2 t 3.89 0.10 0.10 1.30 min. 1.50 1.50 0.30 12.0 0.10 1.75 0.05 5.50 0.10 8.00 0.10 4.00 0.05 2.00 0.05 0.30 v r g m k s n w n m ?101.6 ?330 2.00 +2.00 -0.00 12.40 12mm tape size v r --- --- k s 1.70-2.60 g --- --- h w1 ?13.20 0.30 12.40 h w w1 reel size ?330 unit: mm unit: mm 2.00 k0 t feeding direction +3.00 -0.20 0.10 5.31 +0.1 -0.0 carrier tape reel leader/trailer and orientation trailer tape 300mm min. components tape orientation in pocket leader tape 500mm min. r 0.30 max. d1 p1 p2 b0 a0 p0 d0 e e1 e2 a a unit per reel: 3000pcs
rev. 3.0 may 2018 www.aosmd.com page 13 of 13 AOZ5019 part marking part number code assembly lot code fab code & assembly location year code & week code AOZ5019qi (5x3.5 qfn) z5019qi fa yw lt as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. legal disclaimer alpha and omega semiconductor makes no representati ons or warranties with respect to the accuracy or completeness of the information provid ed herein and takes no liabilities for the conseque nces of use of such information or any product described herein. alpha and omega semiconductor reserves t he right to make changes to such information at any time without further notice. this document does not constitute the grant of any intellectual property rights or representation of non-infringemen t of any third party?s intellectual property rights. life support policy alpha and omega semiconductor products ar e not authorized for use as critical components in life support devices or systems.

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